Micron M25P40 Serial Flash Embedded Memory
Power-Up/Down and Supply Line Decoupling
Power-Up/Down and Supply Line Decoupling
At power-up and power-down, the device must not be selected; that is, chip select (S#)
must follow the voltage applied on VCC until VCC reaches the correct value:
• VCC,min at power-up, and then for a further delay of tVSL
• VSS at power-down
A safe configuration is provided in the SPI Modes section.
To avoid data corruption and inadvertent write operations during power-up, a power-
on-reset (POR) circuit is included. The logic inside the device is held reset while VCC is
less than the POR threshold voltage, VWI – all operations are disabled, and the device
does not respond to any instruction. Moreover, the device ignores the following instruc-
tions until a time delay of tPUW has elapsed after the moment that VCC rises above the
VWI threshold:
• WRITE ENABLE
• PAGE PROGRAM
• SECTOR ERASE
• BULK ERASE
• WRITE STATUS REGISTER
However, the correct operation of the device is not guaranteed if, by this time, VCC is still
below VCC.min. No WRITE STATUS REGISTER, PROGRAM, or ERASE instruction should
be sent until:
t
• PUW after VCC has passed the VWI threshold
t
• VSL after VCC has passed the VCC,min level
If the time, tVSL, has elapsed, after VCC rises above VCC,min, the device can be selected
for READ instructions even if the tPUW delay has not yet fully elapsed.
VPPH must be applied only when VCC is stable and in the VCC,min to VCC,max voltage
range.
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
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