Micron M25P40 Serial Flash Embedded Memory
AC Characteristics
Table 23: AC Specifications (40 MHz, Device Grade 6, VCC[min]=2.3V) (Continued)
Symbol
tSHSL
Alt.
Parameter
Min
100
–
Typ
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
Notes
tCSH S# deselect time
tSHQZ
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX
tHLQZ
tWHSL
tSHWL
tDP
tDIS
tV
tHO
–
Output disable time
–
8
4
Clock LOW to output valid
–
–
8
Output hold time
0
–
–
HOLD# setup time (relative to C)
HOLD# hold time (relative to C)
HOLD# setup time (relative to C)
HOLD# hold time (relative to C)
HOLD# to output LOW-Z
5
–
–
–
5
–
–
–
5
–
–
–
5
–
–
tLZ
tHZ
–
–
–
8
4
4
6
6
4
4
4
HOLD# to output HIGH-Z
–
–
8
WRITE PROTECT setup time
20
100
–
–
–
–
WRITE PROTECT hold time
–
–
–
S# HIGH to DEEP POWER-DOWN mode
S# HIGH to STANDBY without electronic signature read
S# HIGH to STANDBY with electronic signature read
–
3
tRES1
–
–
–
30
30
μs
tRES2
–
–
–
μs
1. Applies to entire table: Maximum frequency in the VCC range 2.3V to 2.7V is 40MHz.
Notes:
2. READ DATA BYTES at HIGHER SPEED, PAGE PROGRAM, SECTOR ERASE, BLOCK ERASE,
DEEP POWER-DOWN, READ ELECTRONIC SIGNATURE, WRITE ENABLE/DISABLE, READ ID,
READ/WRITE STATUS REGISTER
3. The tCH and tCL signals must be greater than or equal to 1/fC.
4. The tCLCH, tCHCL, tSHQZ, tHHQX, tHLQZ, tDP, tRES1, and tRES2 signal values are guaranteed by
characterization, not 100% tested in production.
5. The tCLCH and tCHCLsignals clock rise and fall time values are expressed as a slew-rate.
6. The tWHSL and tSHWLsignals are only applicable as a constraint for a WRITE STATUS REGIS-
TER command when SRWD bit is set at 1.
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
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44
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