M25P20 Serial Flash Embedded Memory
WRITE STATUS REGISTER
Table 7: Status Register Protection Modes
Memory Content
W#
Signal
SRWD
Bit
Protection
Mode (PM)
Status Register
Write Protection
Protected
Area
Unprotected
Area
Notes
1
0
1
0
0
0
1
1
SOFTWARE
PROTECTED mode
(SPM)
Software protection
Commands not
accepted
Commands
accepted
1, 2, 3
HARDWARE
PROTECTED mode
(HPM)
Hardware protection
Commands not
accepted
Commands
accepted
3, 4, 5,
1. Software protection: status register is writable (SRWD, BP1, and BP0 bit values can be
changed) if the WRITE ENABLE command has set the WEL bit.
Notes:
2. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.
3. PAGE PROGRAM and SECTOR ERASE commands can be accepted.
4. Hardware protection: status register is not writable (SRWD, BP1, and BP0 bit values can-
not be changed).
5. PAGE PROGRAM, SECTOR ERASE, AND BULK ERASE commands are not accepted.
When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to
write to the status register provided that the WEL bit has been set previously by a WRITE
ENABLE command, regardless of whether the W# signal is driven HIGH or LOW. When
the status register SRWD bit is set to 1, two cases need to be considered depending on
the state of the W# signal:
• If the W# signal is driven HIGH, it is possible to write to the status register provided
that the WEL bit has been set previously by a WRITE ENABLE command.
• If the W# signal is driven LOW, it is not possible to write to the status register even if
the WEL bit has been set previously by a WRITE ENABLE command. Therefore, at-
tempts to write to the status register are rejected, and are not accepted for execution.
The result is that all the data bytes in the memory area that have been put in SPM by
the status register block protect bits (BP1, BP0) are also hardware protected against
data modification.
Regardless of the order of the two events, the HPM can be entered in either of the fol-
lowing ways:
• Setting the status register SRWD bit after driving the W# signal LOW
• Driving the W# signal LOW after setting the status register SRWD bit.
The only way to exit the HPM is to pull the W# signal HIGH. If the W# signal is perma-
nently tied HIGH, the HPM can never be activated. In this case, only the SPM is availa-
ble, using the status register block protect bits (BP1, BP0).
PDF: 09005aef8456656e
m25p20.pdf - Rev. A 2/13 EN
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