Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Figure 17: Status Register Flowchart
Start
Command Cycle
- Issue Status Register Command
- Address = any device address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
No
SR7 = '1'
Yes
Yes
Yes
- Set/Reset
by WSM
Erase Suspend
See Suspend/Resume Flowchart
SR6 = '1'
No
Program Suspend
See Suspend/Resume Flowchart
SR2 = '1'
No
Yes
Yes
Error
Command Sequence
SR5 = '1'
SR4 = '1'
No
No
Error
Erase Failure
Yes
Error
Program Failure
SR4 = '1'
No
- Set by WSM
- Reset by user
- See Clear Status
Register
Yes
Yes
Error
VPEN < VPENLK
SR3 = '1'
Command
No
Error
Block Locked
SR1 = '1'
No
End
Jan 2011
208032-03
Datasheet
49