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JS28F640J3F75A 参数 Datasheet PDF下载

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型号: JS28F640J3F75A
PDF下载: 下载PDF文件 查看货源
内容描述: Numonyx®嵌入式闪存( J3 65 nm)的单细胞每比特( SBC ) [Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)]
分类和应用: 闪存
文件页数/大小: 66 页 / 2203 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)  
The Status Register indicates when the WSM’s block erase, program, or lock-bit  
configuration operation completes.  
The STS (status) output gives an additional indicator of WSM activity by providing both  
a hardware signal of status (versus software polling) and status masking (interrupt  
masking for background block erase, for example). Status indication using STS  
minimizes both CPU overhead and system power consumption. When configured in  
level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the  
WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates  
that the WSM is ready for a new command, block erase is suspended (and  
programming is inactive), program is suspended, or the device is in reset/power-down  
mode. Additionally, the configuration command allows the STS signal to be configured  
to pulse on completion of programming and/or block erases.  
Three CE signals are used to enable and disable the device. A unique CE logic design  
(see Table 17, “Chip Enable Truth Table for 32-, 64-, 128-Mb” on page 30) reduces  
decoder logic typically required for multi-chip designs. External logic is not required  
when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module.  
The BYTE# signal allows either x8 or x16 read/writes to the device:  
• BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high  
byte.  
• BYTE#-high enables16-bit operation; address A1 becomes the lowest order  
address and address A0 is not used (don’t care).  
Figure 1, “Memory Block Diagram for 32-, 64-, 128-Mbit” on page 11 shows a device  
block diagram.  
When the device is disabled (see Table 17, “Chip Enable Truth Table for 32-, 64-, 128-  
Mb” on page 30), with CEx at VIH and RP# at VIH, the standby mode is enabled. When  
RP# is at VIL, a further power-down mode is enabled which minimizes power  
consumption and provides write protection during reset. A reset time (tPHQV) is  
required from RP# going high until data outputs are valid. Likewise, the device has a  
wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at  
VIL, the WSM is reset and the Status Register is cleared.  
Datasheet  
10  
Jan 2011  
208032-03