512Mb, 1Gb, 2Gb: P30-65nm
AC Read Specifications
Figure 31: Continuous Burst Read with Output Delay
tAVCH
tVLCH tCHAX
CLK
tCHQV
tCHQV
tCHQV
tAVQV
tAVVH
A
tVHAX
tVHVL
ADV#
tELCH
tELVH
tELQV
CE#
OE#
tGLTX
tCHTV
tCHQV
tCHTX
tCHQX
WAIT
DQ
tGLQV
tGLQX
tCHQX
tCHQX
tCHQX
1. WAIT is driven per OE# assertion during synchronous array or nonarray read and can be
configured to assert either during or one data cycle before valid data.
Notes:
2. At the end of a wordline; the delay incurred when a burst access crosses a 16-word
boundary and the starting address is not 4-word boundary aligned.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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