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JS28F512P30BF 参数 Datasheet PDF下载

JS28F512P30BF图片预览
型号: JS28F512P30BF
PDF下载: 下载PDF文件 查看货源
内容描述: 美光并行NOR闪存的嵌入式存储器( P30-65nm ) [Micron Parallel NOR Flash Embedded Memory (P30-65nm)]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 92 页 / 1225 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, 1Gb, 2Gb: P30-65nm  
Bus Operations  
Bus Operations  
CE# LOW and RST# HIGH enable READ operations. The device internally decodes up-  
per address inputs to determine the accessed block. ADV# LOW opens the internal ad-  
dress latches. OE# LOW activates the outputs and gates selected data onto the I/O bus.  
Bus cycles to/from the device conform to standard microprocessor bus operations. Bus  
operations and the logic levels that must be applied to the device control signal inputs  
are shown here.  
Table 5: Bus Operations  
Bus Operation  
RST#  
H
CLK  
ADV#  
CE#  
OE#  
WE#  
H
WAIT  
De-asserted  
Driven  
DQ[15:0]  
Output  
Notes  
READ  
Asynchronous  
Synchronous  
X
L
L
L
L
L
L
-
-
H
Run-  
ning  
H
Output  
WRITE  
H
H
H
L
X
X
X
X
L
L
L
H
H
X
X
L
H
X
X
High-Z  
High-Z  
High-Z  
High-Z  
Input  
High-Z  
High-Z  
High-Z  
1
2
OUTPUT DISABLE  
STANDBY  
X
X
X
H
X
2
RESET  
2, 3  
1. Refer to the Device Command Bus Cycles for valid DQ[15:0] during a WRITE operation.  
2. X = "Don’t Care" (H or L).  
Notes:  
3. RST# must be at VSS ± 0.2V to meet the maximum specified power-down current.  
Read  
To perform a READ operation, RST# and WE# must be de-asserted while CE# and OE#  
are asserted. CE# is the device-select control. When asserted, it enables the device. OE#  
is the data-output control. When asserted, the addressed flash memory data is driven  
onto the I/O bus.  
Write  
To perform a WRITE operation, both CE# and WE# are asserted while RST# and OE# are  
de-asserted. During a WRITE operation, address and data are latched on the rising edge  
of WE# or CE#, whichever occurs first. The Command Bus Cycles table shows the bus  
cycle sequence for each of the supported device commands, while the Command Codes  
and Definitions table describes each command.  
Note: WRITE operations with invalid VCC and/or VPP voltages can produce spurious re-  
sults and should not be attempted.  
Output Disable  
Standby  
When OE# is de-asserted, device outputs DQ[15:0] are disabled and placed in High-Z  
state, WAIT is also placed in High-Z.  
When CE# is de-asserted the device is deselected and placed in standby, substantially  
reducing power consumption. In standby, the data outputs are placed in High-Z, inde-  
pendent of the level placed on OE#. Standby current (ICCS) is the average current meas-  
PDF: 09005aef845667b3  
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
17  
© 2013 Micron Technology, Inc. All rights reserved.