256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
Bus Operations
Bus Operations
Table 6: Bus Operations
Notes 1 and 2 apply to entire table
8-Bit Mode
16-Bit Mode
DQ15/A-1,
DQ[14:0]
Data output Cell address Data output
A[MAX:0],
DQ15/A-1
Operation CE# OE# WE# RST# VPP/WP#
DQ[14:8]
High-Z
DQ[7:0]
A[MAX:0]
READ
L
L
L
H
L
H
H
X
H3
Cell address
WRITE
H
Command
address
High-Z
Data input4
Command
address
Data input4
STANDBY
H
L
X
H
X
H
H
H
H
X
X
X
High-Z
High-Z
High-Z
High-Z
X
X
High-Z
High-Z
OUTPUT
DISABLE
RESET
X
X
X
L
X
X
High-Z
High-Z
X
High-Z
1. Typical glitches of less than 3ns on CE#, WE#, and RST# are ignored by the device and do
not affect bus operations.
Notes:
2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
3. If WP# is LOW, then the highest or the lowest block remains protected, depending on
line item.
4. Data input is required when issuing a command sequence or when performing data
polling or block protection.
Read
Bus READ operations read from the memory cells, registers, or CFI space. To accelerate
the READ operation, the memory array can be read in page mode where data is inter-
nally read and stored in a page buffer.
Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 bus
mode and A[3:0] plus DQ15/A-1 in x8 bus mode. The extended memory blocks and CFI
area do not support page read mode.
A valid bus READ operation involves setting the desired address on the address inputs,
taking CE# and OE# LOW, and holding WE# HIGH. The data I/Os will output the value.
(See AC Characteristics for details about when the output becomes valid.)
Write
Bus WRITE operations write to the command interface. A valid bus WRITE operation
begins by setting the desired address on the address inputs. The address inputs are
latched by the command interface on the falling edge of CE# or WE#, whichever occurs
last. The data I/Os are latched by the command interface on the rising edge of CE# or
WE#, whichever occurs first. OE# must remain HIGH during the entire bus WRITE oper-
ation. (See AC Characteristics for timing requirement details.)
Standby
Driving CE# HIGH in read mode causes the device to enter standby, and data I/Os to be
High-Z. To reduce the supply current to the standby supply current (ICC2), CE# must be
held within VCC ±0.3V. (See DC Characteristics.)
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. B 8/12 EN
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