256Mb and 512Mb (256Mb/256Mb), P30-65nm
Configuration Register
Figure 14: Example Latency Count Setting Using Code 3
t
Data
0
1
2
3
4
CLK
CE#
ADV#
Address
A[MAX:1]
Code 3
High-Z
D[15:0]
Data
R103
End of Wordline Considerations
End of wordline (EOWL) wait states can result when the starting address of the burst op-
eration is not aligned to a 16-word boundary; that is, A[4:1] of the start address does not
equal 0x0. The figure below illustrates the end of wordline wait state(s) that occur after
the first 16-word boundary is reached. The number of data words and wait states is
summarized in the table below.
Figure 15: End of Wordline Timing Diagram
Latency Count
CLK
Address
A[MAX:1]
DQ[15:0]
ADV#
Data
Data
Data
OE#
EOWL
WAIT#
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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