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JS28F256P30B 参数 Datasheet PDF下载

JS28F256P30B图片预览
型号: JS28F256P30B
PDF下载: 下载PDF文件 查看货源
内容描述: 美光并行NOR闪存的嵌入式存储器( P30-65nm ) [Micron Parallel NOR Flash Embedded Memory (P30-65nm)]
分类和应用: 闪存存储
文件页数/大小: 98 页 / 1366 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb and 512Mb (256Mb/256Mb), P30-65nm  
Program Operations  
With adequate continuity testing, programming equipment can rely on the device’s in-  
ternal verification to ensure that the device has programmed properly. This eliminates  
the external post-program verification and its associated overhead.  
Table 14: BEFP Requirements  
Parameter/Issue  
Case temperature  
VCC  
Requirement  
Notes  
TC = 30°C ± 10°C  
Nominal VCC  
VPP  
Driven to VPPH  
Setup and confirm  
Programming  
Target block must be unlocked before issuing the BEFP Setup and Confirm commands.  
The first-word address (WA0) of the block to be programmed must be held constant  
from the setup phase through all data streaming into the target block, until transition  
to the exit phase is desired.  
Buffer alignment  
WA0 must align with the start of an array buffer boundary.  
1
1. Word buffer boundaries in the array are determined by the lowest 9 address bits (0x000  
through 0x1FF). The alignment start point is 0x000.  
Note:  
Table 15: BEFP Considerations  
Parameter/Issue  
Requirement  
Notes  
Cycling  
For optimum performance, cycling must be limited below 50 ERASE cycles per block.  
1
2
Programming blocks BEFP programs one block at a time; all buffer data must fall within a single block.  
Suspend BEFP cannot be suspended.  
Programming the ar- Programming to the array can occur only when the buffer is full.  
ray  
3
1. Some degradation in performance may occur if this limit is exceeded, but the internal  
algorithm continues to work properly.  
Notes:  
2. If the internal address counter increments beyond the block's maximum address, ad-  
dressing wraps around to the beginning of the block.  
3. If the number of words is less than 512, remaining locations must be filled with 0xFFFF.  
BEFP Setup Phase: After receiving the BEFP SETUP and CONFIRM command se-  
quence, SR7 (ready) is cleared, indicating that the device is busy with BEFP algorithm  
startup. A delay before checking SR7 is required to allow the device enough time to per-  
form all of its setups and checks (block lock status, VPP level, etc.). If an error is detected,  
SR4 is set and BEFP operation terminates. If the block was found to be locked, SR1 is  
also set. SR3 is set if the error occurred due to an incorrect VPP level.  
Note: Reading from the device after the BEFP SETUP and CONFIRM command se-  
quence outputs status register data. Do not issue the READ STATUS REGISTER com-  
mand; it will be interpreted as data to be loaded into the buffer.  
BEFP Program/Verify Phase: After the BEFP setup phase has completed, the host pro-  
gramming system must check SR[7,0] to determine the availability of the write buffer  
for data streaming. SR7 cleared indicates the device is busy and the BEFP program/veri-  
fy phase is activated. SR0 indicates the write buffer is available.  
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer  
data programming to the array. For BEFP, the count value for buffer loading is always  
PDF: 09005aef84566799  
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 2013 Micron Technology, Inc. All rights reserved.