256Mb and 512Mb (256Mb/256Mb), P30-65nm
Registers
2. Always clear the Status Register prior to resuming erase operations. It avoids Status Reg-
ister ambiguity when issuing commands during Erase Suspend. If a command sequence
error occurs during an erase-suspend state, the Status Register contains the command
sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes,
possible errors during the erase operation cannot be detected via the Status Register be-
cause it contains the previous error status.
3. A Clear SR command (50h) or Reset must be issued with 15µs delay after the Error bits
(SR4 or SR5) is set during Program/Erase operations.
Clear Status Register
The Clear Status Register command clears the status register. It functions independent
of VPP. The Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits SR[5:3,1]
without clearing them. The Status Register should be cleared before starting a com-
mand sequence to avoid any ambiguity. A device reset also clears the Status Register.
Read Configuration Register
The Read Configuration Register (RCR) is a 16-bit read/write register used to select bus-
read mode (synchronous or asynchronous), and to configure device synchronous burst
read characteristics. To modify RCR settings, use the Configure Read Configuration Reg-
ister command. RCR contents can be examined using the Read Device Identifier com-
mand, and then reading from offset 0x05. On power-up or exit from reset, the RCR de-
faults to asynchronous mode. Details about each RCR bit follow the table.
Table 17: Read Configuration Register
Bit Name
Description
15 Read mode (RM)
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
14:11 Latency count
(LC[3:0])
0000 = Code 0 (reserved)
0001 = Code 1 (reserved)
0010 = Code 2
0011 = Code 3
0100 = Code 4
0110 = Code 6
0111 = Code 7
1000 = Code 8
1001 = Code 9
1010 = Code 10
1011 = Code11
1100 = Code 12
1101 = Code 13
1110 = Code 14
1111 = Code 15 (default)
0101 = Code 5
10 WAIT polarity (WP)
0 = WAIT signal is active low (default)
1 = WAIT signal is active high
9
8
Reserved (R)
Default 0, Non-changeable
WAIT delay (WD)
0 = WAIT deasserted with valid data
1 = WAIT deasserted one data cycle before valid data (default)
7
6
Burst sequence (BS)
Clock edge (CE)
Default 0, Non-changeable
0 = Falling edge
1 = Rising edge (default)
5:4 Reserved (R)
Burst wrap (BW)
Default 0, Non-changeable
3
0 = Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 = No Wrap; Burst accesses do not wrap within burst length (default)
2:0 Burst length (BL[2:0]) 001 = 4-word burst
010 = 8-word burst
011 = 16-word burst
111 = Continuous-word burst (default)
(Other bit settings are reserved)
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. A 1/13 EN
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