256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
Common Flash Interface
Table 20: Device Geometry Definition (Continued)
Address
x16
x8
Data
Description
Value
2Ah
2Bh
54h
56h
000Ah
0000h
Maximum number of bytes in multi-byte program or page =
2n
10241
2Ch
58h
0001h
Number of erase block regions. It specifies the number of
regions containing contiguous erase blocks of the same size.
1
256
2Dh
2Eh
5Ah
5Ch
00FFh
0000h
Erase block region 1 information
Number of identical-size erase blocks = 00FFh + 1 / 01FFh +
1 / 03FFh + 1 / 07FFh + 1
00FFh
0001h
512
00FFh
0003h
1024
2048
128KB
0
00FFh
0007h
2Fh
30h
5Eh
60h
0000h
0002h
Erase block region 1 information
Block size in region 1 = 0200h × 256 bytes
31h
32h
33h
34h
62h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase block region 2 information
Erase block region 3 information
Erase block region 4 information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
0
0
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
1. For x16/x8 mode, the maximum buffer size is 1024/256 bytes, respectively.
Note:
Table 21: Primary Algorithm-Specific Extended Query Table
Note 1 applies to the entire table
Address
x16
40h
41h
42h
43h
44h
45h
x8
Data
0050h
0052h
0049h
0031h
0033h
0018h
Description
Value
"P"
80h
82h
84h
86h
88h
8Ah
Primary algorithm extended query table unique ASCII string “PRI”
"R"
"I"
Major version number, ASCII
Minor version number, ASCII
"1"
"3"
Address sensitive unlock (bits[1:0]):
00 = Required
Required
01 = Not required
Silicon revision number (bits[7:2])
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. B 8/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
51
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