P30-65nm SBC
Table 41: Partition Region 1 Information (Sheet 2 of 2)
Offset(1)
P = 10Ah
Bottom Top
See table below
Address
Description
(Optional flash features and commands)
Bot
Top
136:
137:
138:
139:
13A:
13B:
13C:
Len
(P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information
4
136:
137:
138:
139:
13A:
13B:
13C:
(P+2D)h (P+2D)h
(P+2E)h (P+2E)h
(P+2F)h (P+2F)h
(P+30)h (P+30)h Partition 1 (Erase Block Type 1)
(P+31)h (P+31)h Block erase cycles x 1000
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2
1
(P+32)h (P+32)h Partition 1 (erase block Type 1) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+33)h (P+33)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities
defined in Table 10.
1
6
13D:
13D:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition Region 1 (Erase Block Type 1) Programming Region Information
(P+34)h (P+34)h
(P+35)h (P+35)h
(P+36)h (P+36)h
(P+37)h (P+37)h
(P+38)h (P+38)h
(P+39)h (P+39)h
bits 0–7 = x, 2^x = Programming Region aligned size (
)
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
bytes
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode
bits 24-31 = Reserved
size in bytes
valid
bits 32-39 = z = Control Mode
size in bytes
invalid
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
(P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information
4
(P+3B)h (P+3B)h
(P+3C)h (P+3C)h
(P+3D)h (P+3D)h
(P+3E)h (P+3E)h Partition 1 (Erase Block Type 2)
(P+3F)h (P+3F)h Block erase cycles x 1000
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2
1
(P+40)h (P+40)h Partition 1 (erase block Type 2) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+41)h (P+41)h Partition 1 (erase block Type 2) page mode and synchronous mode capabilities
defined in Table 10.
1
6
14B:
14B:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
Partition Region 1 (Erase Block Type 2) Programming Region Information
(P+42)h (P+42)h
(P+43)h (P+43)h
(P+44)h (P+44)h
(P+45)h (P+45)h
(P+46)h (P+46)h
(P+47)h (P+47)h
bits 0–7 = x, 2^x = Programming Region aligned size (
)
14C:
14D:
14E:
14F:
150:
151:
bytes
14C:
14D:
14E:
14F:
150:
151:
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode
bits 24-31 = Reserved
size in bytes
valid
bits 32-39 = z = Control Mode
size in bytes
invalid
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
Datasheet
70
Apr 2010
Order Number: 208033-02
MICRON [ MICRON TECHNOLOGY ]
