TCN75A
Address Byte
SCL
1
2
3
4
5
6
7
8
9
A
C
K
4.1.6
ACKNOWLEDGE (ACK)
Each receiving device, when addressed, is obliged to
generate an ACK bit after the reception of each byte.
The master device must generate an extra clock pulse
for ACK to be recognized.
The acknowledging device pulls down the SDA line for
t
SU-DATA
before the low-to-high transition of SCL from
the master. SDA also needs to remain pulled down for
t
H-DATA
after a high-to-low transition of SCL.
During read, the master must signal an End-of-Data
(EOD) to the slave by not generating an ACK bit (NAK)
once the last bit has been clocked out of the slave. In
this case, the slave will leave the data line released to
enable the master to generate the Stop condition.
SDA
Start
1
0
0
1 A2 A1 A0
Slave
Address
Address
Code
R/W
TCN75A
Response
FIGURE 4-1:
4.1.5
Device Addressing.
DATA VALID
After the Start condition, each bit of data in
transmission needs to be settled for a time specified by
t
SU-DATA
before SCL toggles from low-to-high (see
©
2006 Microchip Technology Inc.
DS21935C-page 9
MICROCHIP [ MICROCHIP TECHNOLOGY ]
