TC7129
FIGURE 3-1:
STANDARD CIRCUIT
Low Battery
Continuity
V+
5pF
C
O1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DP
4
/OR
21
V
DISP
CONTINUITY
INT OUT
INT IN
V+
22
23
24
25
26
27
ANNUNC
OSC3
OSC1
Display Drive Outputs
TC7129
COMMON
REF LO
RANGE
REF HI
C
REF
+
DGND
C
REF
-
BUFF
IN LO
IN HI
120
kHz
OSC2
DP
1
Crystal
V-
LATCH/
HOLD
DP
3
/UR
DP
2
28
29
30
31
32
33
34
35
36
37
38
39
40
330kΩ
C
INT
0.1µF
C
REF
+
1µF
150kΩ
R
INT
+
9V
R
O
10pF
0.1
µF
C
IF
R
REF
20
kΩ
D
REF
C
RF
0.1µF
C
O2
V+
10kΩ
R
BIAS
–
V
IN
R
IF
100kΩ
+
3.3
Integrating Capacitor (C
INT
)
The charge stored in the integrating capacitor during
the integrate phase is directly proportional to the input
voltage. The primary selection criterion for C
INT
is to
choose a value that gives the highest voltage swing
while remaining within the high linearity portion of the
integrator output range. An integrator swing of 2V is the
recommended value. The capacitor value can be
calculated using the following equation:
The capacitor should have low dielectric absorption to
ensure good integration linearity. Polypropylene and
Teflon capacitors are usually suitable. A good mea-
surement of the dielectric absorption is to connect the
reference capacitor across the inputs by connecting:
Pin to Pin:
20
→
33 (C
REF
+ to IN HI)
30
→
32 (C
REF
- to IN LO)
A reading between 10,000 and 9998 is acceptable;
anything lower indicates unacceptably high dielectric
absorption.
EQUATION 3-3:
C
INT
=
t
INT
x I
INT
V
SWING
3.4
Reference Capacitor (C
REF
)
Where t
INT
is the integration time.
Using the values derived above (assuming 60Hz
operation), the equation becomes:
EQUATION 3-4:
C
INT
= 16.7msec x 13.3µA = 0.1µA
2V
The reference capacitor stores the reference voltage
during several phases of the measurement cycle. Low
leakage is the primary selection criterion for this com-
ponent. The value must be high enough to offset the
effect of stray capacitance at the capacitor terminals. A
value of at least 1µF is recommended.
©
DS21459B-page 8
2002 Microchip Technology Inc.