TC14433/A
3.0
DETAILED DESCRIPTION
The TC14433 CMOS IC becomes a modified dual-
slope A/D with a minimum of external components.
This IC has the customary CMOS digital logic circuitry,
as well as CMOS analog circuitry. It provides the user
with digital functions such as (counters, latches,
multiplexers), and analog functions such as
(operational amplifiers and comparators) on a single
chip. Refer to the Functional Block diagram, Figure 3-3
Features of the TC14433/A include auto-zero, high
input impedances and auto-polarity. Low power
consumption and a wide range of power supply volt-
ages are also advantages of this CMOS device. The
system's auto-zero function compensates for the offset
voltage of the internal amplifiers and comparators. In
this "ratiometric system," the output reading is the ratio
of the unknown voltage to the reference voltage, where
a ratio of 1 is equal to the maximum count of 1999. It
takes approximately 16,000 clock periods to complete
one conversion cycle. Each conversion cycle may be
divided into 6 segments. Figure 3-1 shows the conver-
sion cycle in 6 segments for both positive and negative
inputs.
Segment 1
- The offset capacitor (C
O
), which compen-
sates for the input offset voltages of the buffer and inte-
grator amplifiers, is charged during this period.
However, the integrator capacitor is shorted. This
segment requires 4000 clock periods.
Segment 2
- During this segment, the integrator output
decreases to the comparator threshold voltage. At this
time, a number of counts equivalent to the input offset
voltage of the comparator is stored in the offset latches
for later use in the auto-zero process. The time for this
segment is variable and less than 800 clock periods.
Segment 3
- This segment of the conversion cycle is
the same as Segment 1.
Segment 4
- Segment 4 is an up going ramp cycle with
the unknown input voltage (V
X
as the input to the
integrator.
Figure 4-2
shows
the
equivalent
configuration of the analog section of the TC14433.
The actual configuration of the analog section is
dependent upon the polarity of the input voltage during
the previous conversion cycle.
FIGURE 3-2:
FIGURE 3-1:
INTEGRATOR
WAVEFORMS AT PIN 6
End
Buffer
–
Typical
Positive
Input Voltage
V
X
+
EQUIVALENT CIRCUIT
DIAGRAMS OF THE
ANALOG SECTION
DURING SEGMENT 4 OF
THE TIMING CYCLE
C
1
R1
Integrator
–
+
Comparator
+
–
Start
Time
Segment
Number
1
2
3
4
5
6
V
X
V
X
Typical
Negative
Input Voltage
Segment 5
- This segment is a down-going ramp
period with the reference voltage as the input to the
integrator. Segment 5 of the conversion cycle has a
time equal to the number of counts stored in the offset
storage latches during Segment 2. As a result, the sys-
tem zeros automatically.
Segment 6 -
This is an extension of Segment 5. The
time period for this portion is 4000 clock periods. The
results of the A/D conversion cycle are determined in
this portion of the conversion cycle.
2002 Microchip Technology Inc.
DS21394B-page 7
©
MICROCHIP [ MICROCHIP TECHNOLOGY ]
