TC14433/A
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2.0.
TABLE 2-1:
Pin No.
(24-Pin PDIP)
(24-Pin CERDIP)
(24-Pin SOIC)
1
2
PIN FUNCTION TABLE
Pin No.
Symbol
(28-Pin PLCC)
2
3
V
AG
V
REF
Description
This is the analog ground. It has a high input impedance. The pin determines the
reference level for the unknown input voltage (V
X
) and the reference voltage (V
REF
).
Reference voltage - Full scale output is equal to the voltage applied to V
REF
.
Therefore, full scale voltage of 1.999V requires 2V reference and 199.9mV full scale
requires a 200mV reference. V
REF
functions as system reset also. When switched
to V
EE
, the system is reset to the beginning of the conversion cycle.
The unknown input voltage (V
X
) is measured as a ratio of the reference voltage
(V
REF
) in a rationetric A/D conversion.
This pin is for external components used for the integration function in the dual
slope conversion. Typical values are 0.1µF (mylar) capacitor for C
1
.
R
1
= 470kΩ (resistor) for 2V full scale.
R
1
= 27kΩ (resistor) for 200mV full scale. Clock frequency of 66kHz gives 250msec
conversion time.
These pins are used for connecting the offset correction capacitor.
The recommended value is 0.1µF.
These pins are used for connecting the offset correction capacitor.
The recommended value is 0.1µF.
Display update input pin. When DU is connected to the EOC output, every
conversion is displayed. New data will be strobed into the output latches during the
conversion cycle if a positive edge is received on DU, prior to the ramp down cycle.
When this pin is driven from an external source, the voltage should be referenced
to V
SS
.
Clock input pins. The TC14433 has its own oscillator system clock. Connecting a
single resistor between CLK
1
and CLK
0
sets the clock frequency.
A crystal or OC circuit may be inserted in lieu of a resistor for improved CLK
1
, the
clock input, can be driven from an external clock source, which need only have
standard CMOS output drive. This pin is referenced to V
EE
for external clock inputs.
A 300kΩ resistor yields a clock frequency of about 66kHz. See Section 5.0 Typical
Characteristics. (Also see Figure 4-3 for alternate circuits.)
Negative power current. Connection pin for the most negative supply. Please note
the current for the output drive circuit is returned through V
SS
. Typical supply
current is 0.8mA.
Negative power supply for output circuitry. This pin sets the low voltage level for the
output pins (BCD, Digit Selects, EOC, OR). When connected to analog ground, the
output voltage is from analog ground to V
DD
. If connected to V
EE
, the output swing
is from V
EE
to V
DD
. The recommended operating range for V
SS
is between the
V
DD
-3 volts and V
EE
.
End of conversion output generates a pulse at the end of each conversion cycle.
This generated pulse width is equal to one half the period of the system clock.
Overrange pin. Normally this pin is set high. When V
X
exceeds V
REF
the OR is low.
Digit select pin. The digit select output goes high when the respective digit is
selected. The MSD (1/2 digit turns on immediately after an EOC pulse).
The remaining digits turn on in sequence from MSD to LSD.
To ensure that the BCD data has settled, an inter digit blanking time of two clock
periods is included.
Clock frequency divided by 80 equals multiplex rate. For example, a system clock of
60kHz gives a multiplex rate of 0.8kHz.
See Figure 4-4 for digit select timing diagram.
3
4
5
6
7
8
9
4
5
6
7
9
10
11
V
X
R
1
R
1
/C
1
C
1
CO
1
CO
2
DU
10
11
12
13
CLK
1
CLK
0
12
14
V
EE
13
16
V
SS
14
15
16
17
18
19
20
17
18
19
20
21
23
24
EOC
OR
DS
4
DS
3
DS
2
DS
1
Q
0
2002 Microchip Technology Inc.
DS21394B-page 5
©
MICROCHIP [ MICROCHIP TECHNOLOGY ]
