SST25VF016B
on the SO pin. A ‘0’ indicates the device is busy and a
‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
4.4.6
HARDWARE END-OF-WRITE
DETECTION
The Hardware End-of-Write detection method elimi-
nates the overhead of polling the Busy bit in the Soft-
ware Status Register during an AAI Word program
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status
during AAI Word programming. (see Figure 4-6) The 8-
bit command, 70H, must be executed prior to initiating
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal flash status
To exit AAI Hardware End-of-Write detection, first exe-
cute WRDI instruction, 04H, to reset the Write-Enable-
Latch bit (WEL=0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figures 4-7 and 4-8.
FIGURE 4-6:
ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
MODE 3
MODE 0
0
1
2
3
4 5 6 7
SCK
70
SI
MSB
HIGH IMPEDANCE
SO
1271 EnableSO.0
FIGURE 4-7:
DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
MODE 3
0
1
2
3
4 5 6 7
MODE 0
SCK
80
SI
MSB
HIGH IMPEDANCE
SO
1271 DisableSO.0
2015 Microchip Technology Inc.
DS20005044C-page 11
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