PIC32MX1XX/2XX
REGISTER 10-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
U-0
Bit
30/22/14/6
U-0
Bit
29/21/13/5
U-0
Bit
28/20/12/4
U-0
Bit
27/19/11/3
U-0
Bit
26/18/10/2
U-0
Bit
25/17/9/1
U-0
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
—
R/W-0
—
U-0
—
R/W-0
—
R/W-0
—
R/W-0
—
R/W-0
—
R/W-0
LSPD
RETRYDIS
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-8
Unimplemented:
Read as ‘0’
bit 7
LSPD:
Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
1
= Direct connection to a low-speed device enabled
0
= Direct connection to a low-speed device disabled; hub required with PRE_PID
RETRYDIS:
Retry Disable bit (Host mode and U1EP0 only)
1
= Retry NAK’d transactions disabled
0
= Retry NAK’d transactions enabled; retry done in hardware
Unimplemented:
Read as ‘0’
EPCONDIS:
Bidirectional Endpoint Control bit
If EPTXEN =
1
and EPRXEN =
1:
1
= Disable Endpoint n from Control transfers; only TX and RX transfers allowed
0
= Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed
Otherwise, this bit is ignored.
EPRXEN:
Endpoint Receive Enable bit
1
= Endpoint n receive enabled
0
= Endpoint n receive disabled
EPTXEN:
Endpoint Transmit Enable bit
1
= Endpoint n transmit enabled
0
= Endpoint n transmit disabled
EPSTALL:
Endpoint Stall Status bit
1
= Endpoint n was stalled
0
= Endpoint n was not stalled
EPHSHK:
Endpoint Handshake Enable bit
1
= Endpoint Handshake enabled
0
= Endpoint Handshake disabled (typically used for isochronous endpoints)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS61168D-page 142
Preliminary
©
2011-2012 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
