PIC18F97J60 FAMILY
Pin Diagrams (Continued)
80-Pin TQFP
RE7/ECCP2
(1)
/P2A
(1)
RD0
RE3/P3C
(2)
RE5/P1C
(2)
RE4/P3B
(2)
RE6/P1B
(2)
RE2/P2B
TPOUT+
TPOUT-
V
DDPLL
V
SSPLL
RBIAS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2
RH3
RE1/P2C
RE0/P2D
RB0/INT0/FLT0
RB1/INT1
RB2/INT2
RB3/INT3
MCLR
RG4/CCP5/P1D
V
SS
V
DDCORE
/V
CAP
RF7/SS1
RF6/AN11
RF5/AN10/CV
REF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15/P1B
(2)
RH6/AN14/P1C
(2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
DDRX
TPIN+
TPIN-
V
SSRX
RG0/ECCP3/P3A
RG1/TX2/CK2
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
V
SS
OSC2/CLKO
OSC1/CLKI
V
DD
RB7/KBI3/PGD
RC5/SDO1
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RG2/RX2/DT2
RG3/CCP4/P3D
PIC18F86J60
PIC18F86J65
PIC18F87J60
RH5/AN13/P3B
(2)
RH4/AN12/P3C
(2)
RF1/AN6/C2OUT
RC1/T1OSI/ECCP2
(1)
/P2A
(1)
RC0/T1OSO/T13CKI
RA2/AN2/V
REF
-
RC7/RX1/DT1
RJ4
RA5/AN4
RA1/LEDB/AN1
RA0/LEDA/AN0
RA3/AN3/V
REF
+
Note 1:
2:
The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting.
P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.
RC6/TX1/CK1
AV
DD
ENVREG
V
DD
RA4/T0CKI
AV
SS
RJ5
V
SS
V
DDTX
V
SSTX
RH1
RH0
RD1
RD2
V
DD
V
SS
DS39762E-page 6
©
2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
