PIC18F45J10 FAMILY
FIGURE 24-12:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
83
71
72
78
79
79
78
SCKx
(CKP = 1)
80
MSb
LSb
SDOx
SDIx
bit 6 - - - - - - 1
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
73
Note:
Refer to Figure 24-3 for load conditions.
TABLE 24-16: EXAMPLE SPI™ MODE REQUIREMENTS (CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TCY
—
ns
TSSL2SCL
71
TSCH
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
ns (Note 1)
TSCL
SCKx Input Low Time
(Slave mode)
1.25 TCY + 30
ns
72A
73
40
20
ns (Note 1)
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
40
ns
75
76
77
80
TDOR
TDOF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
—
—
10
—
25
25
50
50
ns
ns
ns
ns
TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
83
TSCH2SSH, SSx ↑ after SCKx Edge
1.5 TCY + 40
—
ns
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
© 2009 Microchip Technology Inc.
DS39682E-page 327