PIC18F45J10 FAMILY
FIGURE 24-11:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 1)
SSx
81
SCKx
(CKP = 0)
71
72
79
78
73
SCKx
(CKP = 1)
80
LSb
MSb
bit 6 - - - - - - 1
SDOx
SDIx
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 24-3 for load conditions.
TABLE 24-15: EXAMPLE SPI™ MODE REQUIREMENTS (CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
73
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
20
—
—
—
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
ns (Note 1)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
40
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDOx Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
81
TDOV2SCH, SDOx Data Output Setup to SCKx Edge
TDOV2SCL
TCY
—
ns
Note 1: Only if Parameter #71A and #72A are used.
DS39682E-page 326
© 2009 Microchip Technology Inc.