欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4520-I/ML 参数 Datasheet PDF下载

PIC18F4520-I/ML图片预览
型号: PIC18F4520-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4520-I/ML的Datasheet PDF文件第138页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第139页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第140页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第141页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第143页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第144页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第145页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第146页  
PIC18F2420/2520/4420/4520  
The assignment of a particular timer to a module is  
15.1 CCP Module Configuration  
determined by the Timer to CCP enable bits in the  
T3CON register (Register 14-1). Both modules may be  
active at any given time and may share the same timer  
resource if they are configured to operate in the same  
mode (Capture/Compare or PWM) at the same time. The  
interactions between the two modules are summarized in  
Figure 15-1 and Figure 15-2. In Timer1 in Asynchronous  
Counter mode, the capture operation will not work.  
Each Capture/Compare/PWM module is associated  
with a control register (generically, CCPxCON) and a  
data register (CCPRx). The data register, in turn, is  
comprised of two 8-bit registers: CCPRxL (low byte)  
and CCPRxH (high byte). All registers are both  
readable and writable.  
15.1.1  
CCP MODULES AND TIMER  
RESOURCES  
15.1.2  
CCP2 PIN ASSIGNMENT  
The CCP modules utilize Timers 1, 2 or 3, depending  
on the mode selected. Timer1 and Timer3 are available  
to modules in Capture or Compare modes, while  
Timer2 is available for modules in PWM mode.  
The pin assignment for CCP2 (Capture input, Compare  
and PWM output) can change, based on device config-  
uration. The CCP2MX Configuration bit determines  
which pin CCP2 is multiplexed to. By default, it is  
assigned to RC1 (CCP2MX = 1). If the Configuration bit  
is cleared, CCP2 is multiplexed with RB3.  
TABLE 15-1: CCP MODE – TIMER  
RESOURCE  
Changing the pin assignment of CCP2 does not auto-  
matically change any requirements for configuring the  
port pin. Users must always verify that the appropriate  
TRIS register is configured correctly for CCP2  
operation, regardless of where it is located.  
CCP/ECCP Mode  
Timer Resource  
Capture  
Compare  
PWM  
Timer1 or Timer3  
Timer1 or Timer3  
Timer2  
TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES  
CCP1 Mode CCP2 Mode  
Interaction  
Capture  
Capture  
Each module can use TMR1 or TMR3 as the time base. The time base can be different  
for each CCP.  
Capture  
Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3  
(depending upon which time base is used). Automatic A/D conversions on trigger event  
can also be done. Operation of CCP1 could be affected if it is using the same timer as a  
time base.  
Compare  
Compare  
Capture  
CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3  
(depending upon which time base is used). Operation of CCP2 could be affected if it is  
using the same timer as a time base.  
Compare Either module can be configured for the Special Event Trigger to reset the time base.  
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if  
both modules are using the same time base.  
Capture  
Compare  
PWM(1)  
PWM(1)  
PWM(1)  
PWM(1)  
PWM(1)  
Capture  
None  
None  
None  
Compare None  
PWM(1)  
Both PWMs will have the same frequency and update rate (TMR2 interrupt).  
Note 1: Includes standard and Enhanced PWM operation.  
DS39631E-page 140  
© 2008 Microchip Technology Inc.  
 复制成功!