PIC18F2420/2520/4420/4520
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values
on page
INTCON
RCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
49
48
52
52
52
52
52
52
52
52
50
50
50
51
51
51
51
51
51
51
51
51
IPEN
SBOREN
ADIF
—
RCIF
RCIE
RCIP
—
PIR1
PSPIF(1)
PSPIE(1)
PSPIP(1)
OSCFIF
OSCFIE
OSCFIP
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
CCP1IF
TMR2IF TMR1IF
PIE1
ADIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
ADIP
PIR2
CMIF
CMIE
CMIP
HLVDIF
TMR3IF
CCP2IF
PIE2
—
HLVDIE TMR3IE CCP2IE
HLVDIP TMR3IP CCP2IP
IPR2
—
TRISB
PORTB Data Direction Register
PORTC Data Direction Register
Timer1 Register Low Byte
TRISC
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
CCPR1L
CCPR1H
CCP1CON
CCPR2L
CCPR2H
CCP2CON
Timer1 Register High Byte
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Timer3 Register High Byte
Timer3 Register Low Byte
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
P1M1(1)
P1M0(1)
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
Capture/Compare/PWM Register 2 Low Byte
Capture/Compare/PWM Register 2 High Byte
—
—
DC2B1
DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
© 2008 Microchip Technology Inc.
DS39631E-page 143
MICROCHIP [ MICROCHIP ]
