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PIC18F4520-I/ML 参数 Datasheet PDF下载

PIC18F4520-I/ML图片预览
型号: PIC18F4520-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
monitoring TMR1L within the interrupt routine until it  
12.7 Considerations in Asynchronous  
increments, and then updating the TMR1H:TMR1L  
register pair while the clock is low, or one-half of the  
period of the clock source. Assuming that Timer1 is  
being used as a Real-Time Clock, the clock source is a  
32.768 kHz crystal oscillator; in this case, one half  
period of the clock is 15.25 μs.  
Counter Mode  
Following a Timer1 interrupt and an update to the  
TMR1 registers, the Timer1 module uses a falling edge  
on its clock source to trigger the next register update on  
the rising edge. If the update is completed after the  
clock input has fallen, the next rising edge will not be  
counted.  
The Real-Time Clock application code in Example 12-1  
shows a typical ISR for Timer1, as well as the optional  
code required if the update cannot be done reliably  
within the required interval.  
If the application can reliably update TMR1 before the  
timer input goes low, no additional action is needed.  
Otherwise, an adjusted update can be performed  
following a later Timer1 increment. This can be done by  
EXAMPLE 12-1:  
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE  
RTCinit  
MOVLW  
MOVWF  
CLRF  
80h  
TMR1H  
TMR1L  
; Preload TMR1 register pair  
; for 1 second overflow  
MOVLW  
MOVWF  
CLRF  
b’00001111’  
T1CON  
secs  
; Configure for external clock,  
; Asynchronous operation, external oscillator  
; Initialize timekeeping registers  
;
CLRF  
mins  
MOVLW  
MOVWF  
BSF  
.12  
hours  
PIE1, TMR1IE  
; Enable Timer1 interrupt  
RETURN  
RTCisr  
; Start ISR here  
; Insert the next 4 lines of code when TMR1  
; can not be reliably updated before clock pulse goes low  
; wait for TMR1L<0> to become clear  
; (may already be clear)  
BTFSC  
BRA  
TMR1L,0  
$-2  
BTFSS  
BRA  
TMR1L,0  
$-2  
; wait for TMR1L<0> to become set  
; TMR1 has just incremented  
; If TMR1 update can be completed before clock pulse goes low  
; Preload for 1 sec overflow  
; Clear interrupt flag  
; Increment seconds  
; 60 seconds elapsed?  
BSF  
BCF  
INCF  
MOVLW  
TMR1H, 7  
PIR1, TMR1IF  
secs, F  
.59  
CPFSGT secs  
RETURN  
; No, done  
CLRF  
INCF  
MOVLW  
secs  
mins, F  
.59  
; Clear seconds  
; Increment minutes  
; 60 minutes elapsed?  
CPFSGT mins  
RETURN  
; No, done  
CLRF  
INCF  
MOVLW  
mins  
hours, F  
.23  
; clear minutes  
; Increment hours  
; 24 hours elapsed?  
CPFSGT hours  
RETURN  
; No, done  
; Reset hours  
; Done  
CLRF  
hours  
RETURN  
© 2008 Microchip Technology Inc.  
DS39631E-page 131  
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