欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4520-I/ML 参数 Datasheet PDF下载

PIC18F4520-I/ML图片预览
型号: PIC18F4520-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4520-I/ML的Datasheet PDF文件第133页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第134页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第135页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第136页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第138页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第139页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第140页浏览型号PIC18F4520-I/ML的Datasheet PDF文件第141页  
PIC18F2420/2520/4420/4520  
A simplified block diagram of the Timer3 module is  
shown in Figure 14-1. A block diagram of the module’s  
operation in Read/Write mode is shown in Figure 14-2.  
14.0 TIMER3 MODULE  
The Timer3 module timer/counter incorporates these  
features:  
The Timer3 module is controlled through the T3CON  
register (Register 14-1). It also selects the clock source  
options for the CCP modules (see Section 15.1.1  
“CCP Modules and Timer Resources” for more  
information).  
• Software selectable operation as a 16-bit timer or  
counter  
• Readable and writable 8-bit registers (TMR3H  
and TMR3L)  
• Selectable clock source (internal or external) with  
device clock or Timer1 oscillator internal options  
• Interrupt-on-overflow  
• Module Reset on CCP Special Event Trigger  
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER  
R/W-0  
RD16  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
T3CCP2  
T3CKPS1  
T3CKPS0  
T3CCP1  
T3SYNC  
TMR3CS  
TMR3ON  
bit 7  
bit 0  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
-n = Value at POR  
bit 7  
RD16: 16-Bit Read/Write Mode Enable bit  
1= Enables register read/write of Timer3 in one 16-bit operation  
0= Enables register read/write of Timer3 in two 8-bit operations  
bit 6,3  
T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits  
1x= Timer3 is the capture/compare clock source for the CCP modules  
01= Timer3 is the capture/compare clock source for CCP2;  
Timer1 is the capture/compare clock source for CCP1  
00= Timer1 is the capture/compare clock source for the CCP modules  
bit 5-4  
bit 2  
T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits  
11= 1:8 Prescale value  
10= 1:4 Prescale value  
01= 1:2 Prescale value  
00= 1:1 Prescale value  
T3SYNC: Timer3 External Clock Input Synchronization Control bit  
(Not usable if the device clock comes from Timer1/Timer3.)  
When TMR3CS = 1:  
1= Do not synchronize external clock input  
0= Synchronize external clock input  
When TMR3CS = 0:  
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.  
bit 1  
bit 0  
TMR3CS: Timer3 Clock Source Select bit  
1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge)  
0= Internal clock (FOSC/4)  
TMR3ON: Timer3 On bit  
1= Enables Timer3  
0= Stops Timer3  
© 2008 Microchip Technology Inc.  
DS39631E-page 135  
 复制成功!