PIC18F2480/2580/4480/4580
peripheral functions. The reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
6.3.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 6-1 and Table 6-2.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
TABLE 6-1:
SPECIAL FUNCTION REGISTER MAP FOR
PIC18F2480/2580/4480/4580 DEVICES
Address
Name
Address
Name
Address
Name
Address
Name
(3)
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
TOSU
TOSH
FDFh
FDEh
INDF2
FBFh
FBEh
FBDh
FBCh
FBBh
ECCPR1H
ECCPR1L
CCP1CON
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
IPR1
(3)
(3)
POSTINC2
PIR1
TOSL
FDDh POSTDEC2
PIE1
(3)
(1)
STKPTR
PCLATU
PCLATH
PCL
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PREINC2
CCPR2H
—
(3)
(1)
PLUSW2
CCPR2L
OSCTUNE
(1)
FSR2H
FSR2L
FBAh ECCP1CON
—
—
—
—
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
—
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
STATUS
TMR0H
TMR0L
BAUDCON
ECCP1DEL
(1)
(1)
ECCP1AS
TRISE
(1)
(1)
T0CON
—
CVRCON
TRISD
CMCON
TMR3H
TMR3L
T3CON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
—
TRISC
TRISB
TRISA
—
OSCCON
HLVDCON
WDTCON
RCON
—
(3)
INDF0
TMR1H
TMR1L
—
(3)
POSTINC0
POSTDEC0
—
(3)
(1)
T1CON
TMR2
LATE
(3)
(1)
PREINC0
LATD
(3)
PLUSW0
FSR0H
FSR0L
WREG
PR2
LATC
LATB
LATA
—
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
EEADR
EEDATA
(3)
(3)
INDF1
EECON2
—
(3)
(3)
POSTINC1
EECON1
IPR3
—
POSTDEC1
—
(3)
PREINC1
PIR3
PORTE
(3)
(1)
PLUSW1
FSR1H
FSR1L
BSR
PIE3
PORTD
IPR2
PORTC
PORTB
PORTA
PIR2
PIE2
Note 1: Registers available only on PIC18F4X80 devices; otherwise, the registers read as ‘0’.
2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties.
3: This is not a physical register.
© 2009 Microchip Technology Inc.
DS39637D-page 77
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