PIC18F2480/2580/4480/4580
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval,
TCSD, following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
4.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode where the primary clock source
is not stopped; and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
TABLE 4-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
Before Wake-up
Clock Source
After Wake-up
Clock Ready Status
bit (OSCCON)
Exit Delay
LP, XT, HS
HSPLL
OSTS
Primary Device Clock
(PRI_IDLE mode)
(2)
EC, RC
TCSD
INTRC(1)
INTOSC(3)
LP, XT, HS
HSPLL
—
IOFS
(4)
TOST
(4)
OSTS
TOST + trc
T1OSC or INTRC(1)
EC, RC
(2)
TCSD
INTRC(1)
INTOSC(3)
LP, XT, HS
HSPLL
—
(5)
TIOBST
IOFS
(5)
TOST
(4)
OSTS
TOST + trc
INTOSC(3)
EC, RC
(2)
TCSD
INTRC(1)
INTOSC(3)
LP, XT, HS
HSPLL
—
None
IOFS
(4)
TOST
(4)
OSTS
TOST + trc
None
(Sleep mode)
EC, RC
(2)
TCSD
INTRC(1)
INTOSC(3)
—
(5)
TIOBST
IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 4.4 “Idle Modes”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is
also designated as TPLL.
5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.
DS39637D-page 46
© 2009 Microchip Technology Inc.
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