PIC18F2480/2580/4480/4580
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
18.4.7
BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 18-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Table 18-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 18-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 18-3: I2C™ CLOCK RATE W/BRG
FSCL
FCY
FCY*2
BRG Value
(2 Rollovers of BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
19h
20h
64h
0Ah
0Dh
28h
03h
0Ah
400 kHz
312.5 kHz
100 kHz
400 kHz
308 kHz
100 kHz
333 kHz
100 kHz
© 2009 Microchip Technology Inc.
DS39637D-page 217
MICROCHIP [ MICROCHIP ]
