PIC18F2480/2580/4480/4580
cycle (Fosc/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator if enabled.
15.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
As with Timer1, the RC1/T1OSI and RC0/T1OSO/
T13CKI pins become inputs when the Timer1 oscillator
is enabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
FIGURE 15-1:
TIMER3 BLOCK DIAGRAM
Timer1 Oscillator
1
T1OSO/T13CKI
T1OSI
1
0
Synchronize
Prescaler
FOSC/4
Internal
Clock
0
Detect
1, 2, 4, 8
2
Sleep Input
T1OSCEN(1)
TMR3CS
Timer3
On/Off
T3CKPS<1:0>
T3SYNC
TMR3ON
CCP/ECCP Special Event Trigger
T3ECCP1
Clear TMR3
Set
TMR3
High Byte
TMR3L
TMR3IF
on Overflow
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
FIGURE 15-2:
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 clock input
1
0
T1OSO/T13CKI
T1OSI
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
Sleep Input
T1OSCEN(1)
T3CKPS<1:0>
T3SYNC
Timer3
On/Off
TMR3CS
TMR3ON
CCP/ECCP Special Event Trigger
T3ECCP1
Clear TMR3
Set
TMR3
High Byte
TMR3L
TMR3IF
on Overflow
8
Read TMR1L
Write TMR1L
8
8
TMR3H
8
8
Internal Data Bus
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
DS39637D-page 164
© 2009 Microchip Technology Inc.
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