PIC18F2480/2580/4480/4580
14.2 Timer2 Interrupt
14.3 TMR2 Output
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match)
provides the input for the 4-bit output counter/post-
scaler. This counter generates the TMR2 match inter-
rupt flag which is latched in TMR2IF (PIR1<1>). The
interrupt is enabled by setting the TMR2 Match Inter-
rupt Enable bit, TMR2IE (PIE1<1>).
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode. Addi-
tional information is provided in Section 18.0 “Master
Synchronous Serial Port (MSSP) Module”.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 14-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR2IF
Postscaler
T2OUTPS<3:0>
2
TMR2 Output
T2CKPS<1:0>
(to PWM or MSSP)
TMR2/PR2
Match
Reset
1:1, 1:4, 1:16
Prescaler
Comparator
PR2
FOSC/4
TMR2
8
8
8
Internal Data Bus
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
55
58
58
58
56
56
56
PIR1
PIE1
IPR1
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR1IF
TMR1IE
TMR1IP
TXIE
TXIP
TMR2 Timer2 Register
T2CON
PR2
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on PIC18F2X80 devices; always maintain these bits clear.
DS39637D-page 162
© 2009 Microchip Technology Inc.
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