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PIC18F4520-I/PT 参数 Datasheet PDF下载

PIC18F4520-I/PT图片预览
型号: PIC18F4520-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
9.1  
INTCON Registers  
Note:  
Interrupt flag bits are set when an interrupt  
condition occurs, regardless of the state of  
its corresponding enable bit or the global  
enable bit. User software should ensure  
the appropriate interrupt flag bits are clear  
prior to enabling an interrupt. This feature  
allows for software polling.  
The INTCON registers are readable and writable  
registers, which contain various enable, priority and  
flag bits.  
REGISTER 9-1:  
INTCON: INTERRUPT CONTROL REGISTER  
R/W-0  
R/W-0  
PEIE/GIEL  
R/W-0  
R/W-0  
R/W-0  
RBIE  
R/W-0  
R/W-0  
INT0IF  
R/W-x  
RBIF(1)  
GIE/GIEH  
bit 7  
TMR0IE  
INT0IE  
TMR0IF  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
GIE/GIEH: Global Interrupt Enable bit  
When IPEN = 0:  
1= Enables all unmasked interrupts  
0= Disables all interrupts  
When IPEN = 1:  
1= Enables all high-priority interrupts  
0= Disables all interrupts  
bit 6  
PEIE/GIEL: Peripheral Interrupt Enable bit  
When IPEN = 0:  
1= Enables all unmasked peripheral interrupts  
0= Disables all peripheral interrupts  
When IPEN = 1:  
1= Enables all low-priority peripheral interrupts  
0= Disables all low-priority peripheral interrupts  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
TMR0IE: TMR0 Overflow Interrupt Enable bit  
1= Enables the TMR0 overflow interrupt  
0= Disables the TMR0 overflow interrupt  
INT0IE: INT0 External Interrupt Enable bit  
1= Enables the INT0 external interrupt  
0= Disables the INT0 external interrupt  
RBIE: RB Port Change Interrupt Enable bit  
1= Enables the RB port change interrupt  
0= Disables the RB port change interrupt  
TMR0IF: TMR0 Overflow Interrupt Flag bit  
1= TMR0 register has overflowed (must be cleared in software)  
0= TMR0 register did not overflow  
INT0IF: INT0 External Interrupt Flag bit  
1= The INT0 external interrupt occurred (must be cleared in software)  
0= The INT0 external interrupt did not occur  
RBIF: RB Port Change Interrupt Flag bit(1)  
1= At least one of the RB<7:4> pins changed state (must be cleared in software)  
0= None of the RB<7:4> pins have changed state  
Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and  
allow the bit to be cleared.  
© 2008 Microchip Technology Inc.  
DS39631E-page 93  
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