PIC18F2420/2520/4420/4520
FIGURE 9-1:
PIC18 INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
SSPIF
SSPIE
SSPIP
GIE/GIEH
ADIF
ADIE
ADIP
IPEN
IPEN
RCIF
RCIE
RCIP
PEIE/GIEL
IPEN
Additional Peripheral Interrupts
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
SSPIF
SSPIE
SSPIP
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
ADIF
ADIE
ADIP
RBIF
RBIE
RBIP
RCIF
RCIE
RCIP
GIE/GIEH
PEIE/GIE
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS39631E-page 92
© 2008 Microchip Technology Inc.