PIC18F2420/2520/4420/4520
REGISTER 6-1:
R/W-x
EEPGD
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
S = Settable bit (cannot be cleared in software)
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
EECON1: EEPROM CONTROL REGISTER 1
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
WRERR
(1)
R/W-0
WREN
R/S-0
WR
R/S-0
RD
bit 0
EEPGD:
Flash Program or Data EEPROM Memory Select bit
1
= Access Flash program memory
0
= Access data EEPROM memory
CFGS:
Flash Program/Data EEPROM or Configuration Select bit
1
= Access Configuration registers
0
= Access Flash program or data EEPROM memory
Unimplemented:
Read as ‘0’
FREE:
Flash Row Erase Enable bit
1
= Erase the program memory row addressed by TBLPTR on the next WR command (cleared by
completion of erase operation)
0
= Perform write only
WRERR:
Flash Program/Data EEPROM Error Flag bit
(1)
1
= A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0
= The write operation completed
WREN:
Flash Program/Data EEPROM Write Enable bit
1
= Allows write cycles to Flash program/data EEPROM
0
= Inhibits write cycles to Flash program/data EEPROM
WR:
Write Control bit
1
= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0
= Write cycle to the EEPROM is complete
RD:
Read Control bit
1
= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software. RD bit cannot be set when EEPGD =
1
or CFGS =
1.)
0
= Does not initiate an EEPROM read
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
©
2008 Microchip Technology Inc.
DS39631E-page 75
MICROCHIP [ MICROCHIP TECHNOLOGY ]
