PIC18F2420/2520/4420/4520
TABLE 5-2:
File Name
TOSU
PIC18F2420/2520/4420/4520 REGISTER FILE SUMMARY
Value on
POR, BOR on page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 49, 54
0000 0000 49, 54
0000 0000 49, 54
00-0 0000 49, 55
---0 0000 49, 54
0000 0000 49, 54
0000 0000 49, 54
--00 0000 49, 76
0000 0000 49, 76
0000 0000 49, 76
0000 0000 49, 76
xxxx xxxx 49, 89
xxxx xxxx 49, 89
0000 000x 49, 93
1111 -1-1 49, 94
11-0 0-00 49, 95
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
—
SP4
SP3
SP2
SP1
SP0
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH
RBPU
PEIE/GIEL
INTEDG0
INT1IP
TMR0IE
INTEDG1
—
INT0IE
INTEDG2
INT2IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
49, 69
49, 69
49, 69
49, 69
49, 69
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
FSR0H
FSR0L
WREG
INDF1
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000 49, 69
xxxx xxxx 49, 69
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
xxxx xxxx
N/A
49
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
49, 69
49, 69
49, 69
49, 69
49, 69
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
N/A
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000 50, 69
xxxx xxxx 50, 69
---- 0000 50, 59
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
N/A
N/A
N/A
N/A
50, 69
50, 69
50, 69
50, 69
50, 69
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
FSR2H
FSR2L
STATUS
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000 50, 69
xxxx xxxx 50, 69
---x xxxx 50, 67
Indirect Data Memory Address Pointer 2 Low Byte
—
—
—
N
OV
Z
DC
C
Legend:
x= unknown, u= unchanged, —= unimplemented, q= value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1:
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2:
3:
4:
5:
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
DS39631E-page 64
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
