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PIC18F4520-I/PT 参数 Datasheet PDF下载

PIC18F4520-I/PT图片预览
型号: PIC18F4520-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
CALLW  
Subroutine Call Using WREG  
MOVSF  
Move Indexed to f  
Syntax:  
CALLW  
None  
Syntax:  
MOVSF [z ], f  
s
d
Operands:  
Operation:  
Operands:  
0 z 127  
s
0 f 4095  
d
(PC + 2) TOS,  
(W) PCL,  
Operation:  
((FSR2) + z ) f  
s
d
(PCLATH) PCH,  
(PCLATU) PCU  
Status Affected:  
None  
Encoding:  
1st word (source)  
2nd word (destin.)  
Status Affected:  
Encoding:  
None  
1110  
1111  
1011  
ffff  
0zzz  
ffff  
zzzz  
ffff  
s
0000  
0000  
0001  
0100  
d
Description  
First, the return address (PC + 2) is  
pushed onto the return stack. Next, the  
contents of W are written to PCL; the  
existing value is discarded. Then, the  
contents of PCLATH and PCLATU are  
latched into PCH and PCU,  
respectively. The second cycle is  
executed as a NOPinstruction while the  
new next instruction is fetched.  
Description:  
The contents of the source register are  
moved to destination register ‘f ’. The  
d
actual address of the source register is  
determined by adding the 7-bit literal  
offset ‘z ’ in the first word to the value of  
s
FSR2. The address of the destination  
register is specified by the 12-bit literal  
‘f ’ in the second word. Both addresses  
d
can be anywhere in the 4096-byte data  
space (000h to FFFh).  
The MOVSFinstruction cannot use the  
PCL, TOSU, TOSH or TOSL as the  
destination register.  
If the resultant source address points to  
an indirect addressing register, the  
value returned will be 00h.  
Unlike CALL, there is no option to  
update W, STATUS or BSR.  
Words:  
Cycles:  
1
2
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Words:  
Cycles:  
2
2
Decode  
Read  
WREG  
PUSH PC to  
stack  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Decode  
Determine  
Determine  
Read  
source addr source addr source reg  
Example:  
HERE  
CALLW  
Decode  
No  
operation  
No  
operation  
Write  
register ‘f’  
(dest)  
Before Instruction  
PC  
=
address (HERE)  
PCLATH =  
PCLATU =  
10h  
00h  
06h  
No dummy  
read  
W
=
After Instruction  
PC  
TOS  
=
=
001006h  
address (HERE + 2)  
Example:  
MOVSF  
[05h], REG2  
PCLATH =  
PCLATU =  
10h  
00h  
06h  
Before Instruction  
FSR2  
=
80h  
33h  
W
=
Contents  
of 85h  
REG2  
=
=
11h  
After Instruction  
FSR2  
=
80h  
Contents  
of 85h  
REG2  
=
=
33h  
33h  
© 2008 Microchip Technology Inc.  
DS39631E-page 311