PIC18F2420/2520/4420/4520
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL
TMR0IE
—
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
49
48
52
52
52
52
52
52
52
52
52
50
50
50
50
50
50
51
51
51
51
51
51
51
51
IPEN
PSPIF
SBOREN
ADIF
BOR
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
PIE1
PSPIE
ADIE
IPR1
PSPIP
ADIP
PIR2
OSCFIF
OSCFIE
OSCFIP
CMIF
CMIE
CMIP
PIE2
—
IPR2
—
TRISB
TRISC
TRISD
TMR1L
TMR1H
T1CON
TMR2
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Timer1 Register Low Byte
Timer1 Register High Byte
RD16
Timer2 Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
T1RUN
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
T2CON
PR2
—
Timer2 Period Register
Timer3 Register Low Byte
Timer3 Register High Byte
TMR3L
TMR3H
T3CON
CCPR1L
CCPR1H
CCP1CON
RD16
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1
T3SYNC TMR3CS TMR3ON
CCP1M2 CCP1M1 CCP1M0
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
(1)
(1)
P1M1
P1M0
DC1B1
DC1B0
CCP1M3
PSSAC1
(1)
(1)
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
PSSAC0 PSSBD1
PSSBD0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PWM1CON
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
DS39631E-page 160
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
