PIC18F2420/2520/4420/4520
15.3.2
TIMER1/TIMER3 MODE SELECTION
15.3 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
15.3.3
SOFTWARE INTERRUPT MODE
• driven low
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the corresponding CCPx pin is
not affected. A CCP interrupt is generated when the
CCPxIF interrupt flag is set while the CCPxIE bit is set.
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
15.3.4
SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM<3:0> = 1011).
15.3.1
CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCP2CON register will force
the RB3 or RC1 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTB or
PORTC I/O data latch.
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
Period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D Converter
must already be enabled.
FIGURE 15-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger
(Timer1/Timer3 Reset)
Set CCP1IF
CCPR1H
CCPR1L
CCP1 pin
S
R
Q
Output
Logic
Compare
Match
Comparator
TRIS
Output Enable
4
CCP1CON<3:0>
TMR1H
TMR3H
TMR1L
TMR3L
0
1
0
1
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
T3CCP1
T3CCP2
Set CCP2IF
CCP2 pin
S
R
Q
Compare
Match
Output
Logic
Comparator
TRIS
Output Enable
4
CCPR2H
CCPR2L
CCP2CON<3:0>
DS39631E-page 142
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
