PIC18F2420/2520/4420/4520
15.2
Capture Mode
15.2.3
SOFTWARE INTERRUPT
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the corresponding CCPx pin.
An event is defined as one of the following:
•
•
•
•
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false inter-
rupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
15.2.4
CCP PRESCALER
The event is selected by the mode select bits,
CCPxM<3:0> (CCPxCON<3:0>). When a capture is
made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value is overwritten by the new captured value.
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCPxM<3:0>). Whenever the
CCP module is turned off, or Capture mode is disabled,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
15.2.1
CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
Note:
If RB3/CCP2 or RC1/CCP2 is configured
as an output, a write to the port can cause
a capture condition.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP2 SHOWN)
;
;
;
;
;
;
Turn CCP module off
Load WREG with the
new prescaler mode
value and CCP ON
Load CCP2CON with
this value
15.2.2
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation will not work. The timer to be
used with each CCP module is selected in the T3CON
register (see
CLRF
MOVLW
CCP2CON
NEW_CAPT_PS
MOVWF
CCP2CON
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set CCP1IF
T3CCP2
TMR3H
TMR3
Enable
CCPR1H
TMR1
Enable
TMR1H
Set CCP2IF
TMR1L
CCPR1L
TMR3L
CCP1 pin
Prescaler
÷
1, 4, 16
and
Edge Detect
T3CCP2
CCP1CON<3:0>
Q1:Q4
CCP2CON<3:0>
4
4
4
T3CCP1
T3CCP2
TMR3H
TMR3
Enable
CCPR2H
TMR1
Enable
TMR3L
CCP2 pin
Prescaler
÷
1, 4, 16
and
Edge Detect
CCPR2L
T3CCP2
T3CCP1
TMR1H
TMR1L
©
2008 Microchip Technology Inc.
DS39631E-page 141
MICROCHIP [ MICROCHIP TECHNOLOGY ]
