PIC18F2420/2520/4420/4520
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES<3:0>).
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES<3:0> = ARG1H:ARG1L • ARG2H:ARG2L
16
= (ARG1H • ARG2H • 2 ) +
(ARG1H • ARG2L • 2 ) +
(ARG1L • ARG2H • 2 ) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 2 ) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 2
8
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
8
16
RES<3:0>
=
=
ARG1H:ARG1L • ARG2H:ARG2L
16
)
16
(ARG1H • ARG2H • 2 ) +
8
(ARG1H • ARG2L • 2 ) +
8
(ARG1L • ARG2H • 2 ) +
EXAMPLE 8-4:
16 x 16 SIGNED MULTIPLY
ROUTINE
(ARG1L • ARG2L)
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L->
; PRODH:PRODL
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
; ARG1H * ARG2H ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H->
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1L, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1L * ARG2H ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; PRODH:PRODL
;
; Add cross
; products
;
;
;
;
MOVF
ADDWF
MOVF
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
PRODL, W
RES1, F
PRODH, W
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L->
; PRODH:PRODL
;
; Add cross
; products
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES<3:0>). To account for the sign bits of the argu-
ments, the MSb for each argument pair is tested and
the appropriate subtractions are done.
ARG1H, W
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39631E-page 90
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
