PIC18F2420/2520/4420/4520
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
TABLE 3-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
Before Wake-up
Clock Source
After Wake-up
Clock Ready Status
Bit (OSCCON)
Exit Delay
LP, XT, HS
HSPLL
OSTS
IOFS
OSTS
IOFS
OSTS
IOFS
OSTS
IOFS
Primary Device Clock
(PRI_IDLE mode)
(1)
TCSD
EC, RC
INTOSC(2)
LP, XT, HS
HSPLL
(3)
TOST
(3)
TOST + trc
T1OSC or INTRC(1)
(1)
EC, RC
TCSD
(1)
INTOSC(2)
LP, XT, HS
HSPLL
TCSD
(3)
TOST
(3)
TOST + trc
INTOSC(2)
(1)
EC, RC
TCSD
INTOSC(2)
LP, XT, HS
HSPLL
TCSD
(1)
(3)
TOST
(3)
TOST + trc
None
(Sleep mode)
(1)
EC, RC
INTOSC(2)
TCSD
(1)
TCSD
Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 3.4 “Idle Modes”). On Reset, INTOSC defaults to 1 MHz.
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL lock-out timer (parameter F12); it is also
designated as TPLL.
DS39631E-page 40
Advance Information
© 2008 Microchip Technology Inc.
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