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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
On all exits from Idle or Sleep modes by interrupt, code  
execution branches to the interrupt vector if the GIE/  
GIEH bit (INTCON<7>) is set. Otherwise, code execu-  
tion continues or resumes without branching (see  
Section 9.0 “Interrupts”).  
3.4.3  
RC_IDLE MODE  
In RC_IDLE mode, the CPU is disabled but the periph-  
erals continue to be clocked from the internal oscillator  
block using the INTOSC multiplexer. This mode allows  
for controllable power conservation during Idle periods.  
A fixed delay of interval TCSD following the wake event  
is required when leaving Sleep and Idle modes. This  
delay is required for the CPU to prepare for execution.  
Instruction execution resumes on the first clock cycle  
following this delay.  
From RC_RUN, this mode is entered by setting the  
IDLEN bit and executing a SLEEP instruction. If the  
device is in another Run mode, first set IDLEN, then set  
the SCS1 bit and execute SLEEP. Although its value is  
ignored, it is recommended that SCS0 also be cleared;  
this is to maintain software compatibility with future  
devices. The INTOSC multiplexer may be used to  
select a higher clock frequency by modifying the IRCF  
bits before executing the SLEEPinstruction. When the  
clock source is switched to the INTOSC multiplexer, the  
primary oscillator is shut down and the OSTS bit is  
cleared.  
3.5.2  
EXIT BY WDT TIME-OUT  
A WDT time-out will cause different actions depending  
on which power-managed mode the device is in when  
the time-out occurs.  
If the device is not executing code (all Idle modes and  
Sleep mode), the time-out will result in an exit from the  
power-managed mode (see Section 3.2 “Run  
Modes” and Section 3.3 “Sleep Mode”). If the device  
is executing code (all Run modes), the time-out will  
result in a WDT Reset (see Section 23.2 “Watchdog  
Timer (WDT)”).  
If the IRCF bits are set to any non-zero value, or the  
INTSRC bit is set, the INTOSC output is enabled. The  
IOFS bit becomes set, after the INTOSC output  
becomes stable, after an interval of TIOBST  
(parameter 39, Table 26-10). Clocks to the peripherals  
continue while the INTOSC source stabilizes. If the  
IRCF bits were previously at a non-zero value, or  
INTSRC was set before the SLEEPinstruction was exe-  
cuted and the INTOSC source was already stable, the  
IOFS bit will remain set. If the IRCF bits and INTSRC  
are all clear, the INTOSC output will not be enabled, the  
IOFS bit will remain clear and there will be no indication  
of the current clock source.  
The WDT timer and postscaler are cleared by  
executing a SLEEPor CLRWDTinstruction, the loss of a  
currently selected clock source (if the Fail-Safe Clock  
Monitor is enabled) and modifying the IRCF bits in the  
OSCCON register if the internal oscillator block is the  
device clock source.  
3.5.3  
EXIT BY RESET  
When a wake event occurs, the peripherals continue to  
be clocked from the INTOSC multiplexer. After a delay of  
TCSD following the wake event, the CPU begins  
executing code being clocked by the INTOSC multi-  
plexer. The IDLEN and SCS bits are not affected by the  
wake-up. The INTRC source will continue to run if either  
the WDT or the Fail-Safe Clock Monitor is enabled.  
Normally, the device is held in Reset by the Oscillator  
Start-up Timer (OST) until the primary clock becomes  
ready. At that time, the OSTS bit is set and the device  
begins executing code. If the internal oscillator block is  
the new clock source, the IOFS bit is set instead.  
The exit delay time from Reset to the start of code  
execution depends on both the clock sources before  
and after the wake-up and the type of oscillator if the  
new clock source is the primary clock. Exit delays are  
summarized in Table 3-2.  
3.5  
Exiting Idle and Sleep Modes  
An exit from Sleep mode or any of the Idle modes is  
triggered by an interrupt, a Reset or a WDT time-out.  
This section discusses the triggers that cause exits  
from power-managed modes. The clocking subsystem  
actions are discussed in each of the power-managed  
modes (see Section 3.2 “Run Modes”, Section 3.3  
“Sleep Mode” and Section 3.4 “Idle Modes”).  
Code execution can begin before the primary clock  
becomes ready. If either the Two-Speed Start-up (see  
Section 23.3 “Two-Speed Start-up”) or Fail-Safe  
Clock Monitor (see Section 23.4 “Fail-Safe Clock  
Monitor”) is enabled, the device may begin execution  
as soon as the Reset source has cleared. Execution is  
clocked by the INTOSC multiplexer driven by the inter-  
nal oscillator block. Execution is clocked by the internal  
oscillator block until either the primary clock becomes  
ready or a power-managed mode is entered before the  
primary clock becomes ready; the primary clock is then  
shut down.  
3.5.1  
EXIT BY INTERRUPT  
Any of the available interrupt sources can cause the  
device to exit from an Idle mode or the Sleep mode to  
a Run mode. To enable this functionality, an interrupt  
source must be enabled by setting its enable bit in one  
of the INTCON or PIE registers. The exit sequence is  
initiated when the corresponding interrupt flag bit is set.  
© 2008 Microchip Technology Inc.  
Advance Information  
DS39631E-page 39  
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