PIC18F45J10 FAMILY
FIGURE 24-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 24-3 for load conditions.
FIGURE 24-7:
BROWN-OUT RESET TIMING
BVDD
VDD
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
TABLE 24-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
TWDT
MCLR Pulse Width (low)
2
—
—
μs
31
Watchdog Timer Time-out Period
(no postscaler)
2.8
4.1
5.4
ms
32
33
34
TOST
Oscillation Start-up Timer Period
1024 TOSC
46.2
—
66
2
1024 TOSC
85.8
—
ms
μs
TOSC = OSC1 period
TPWRT Power-up Timer Period
TIOZ
I/O High-Impedance from MCLR
—
—
Low or Watchdog Timer Reset
38
TCSD
CPU Start-up Time
—
200
—
μs
DS39682E-page 322
© 2009 Microchip Technology Inc.
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