PIC18F45J10 FAMILY
FIGURE 24-5:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
14
12
19
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 24-3 for load conditions.
Note:
TABLE 24-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TOSH2CKL OSC1 ↑ to CLKO ↓
TOSH2CKH OSC1 ↑ to CLKO ↑
—
75
75
15
15
—
—
—
50
—
—
—
200
200
30
ns
ns
ns
ns
11
—
12
13
14
15
16
17
18
18A
19
TCKR
TCKF
CLKO Rise Time
CLKO Fall Time
—
—
30
TCKL2IOV CLKO ↓ to Port Out Valid
TIOV2CKH Port In Valid before CLKO ↑
TCKH2IOI Port In Hold after CLKO ↑
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
0.5 TCY + 20 ns
0.25 TCY + 25
—
—
ns
ns
ns
ns
ns
ns
0
—
150
—
TOSH2IOI OSC1 ↑ (Q2 cycle) to Port Input Invalid
100
200
0
(I/O in hold time)
—
TIOV2OSH Port Input Valid to OSC1 ↑
—
(I/O in setup time)
20
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
—
—
—
—
6
5
ns
ns
ns
ns
21
Port Output Fall Time
22†
23†
INTx pin High or Low Time
RB<7:4> Change INTx High or Low Time
TCY
TCY
—
—
†
These parameters are asynchronous events not related to any internal clock edges.
© 2009 Microchip Technology Inc.
DS39682E-page 321
MICROCHIP [ MICROCHIP ]
