PIC18F45J10 FAMILY
TABLE 5-2:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
BAUDCON
ECCP1DEL
ECCP1AS
CVRCON
CMCON
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
01-0 0-00
0000 0000
0000 0000
0000 0000
0000 0111
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0010
0000 000x
0000 0000
---0 x00-
11-- ----
00-- ----
00-- ----
11-- 1--1
00-- 0--0
00-- 0--0
1111 1111
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
01-0 0-00
0000 0000
0000 0000
0000 0000
0000 0111
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0010
0000 000x
0000 0000
---0 x00-
11-- ----
00-- ----
00-- ----
11-- 1--1
00-- 0--0
00-- 0--0
1111 1111
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uu-u u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuu-
uu-- ----
uu-- ----(3)
uu-- ----
uu-- u--u
uu-- u--u(3)
uu-- u--u
uuuu uuuu
uuuu uuuu(3)
uuuu uuuu
RCSTA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
© 2009 Microchip Technology Inc.
DS39682E-page 49
MICROCHIP [ MICROCHIP ]
