PIC18F45J10 FAMILY
FIGURE 24-18:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TX/CK
pin
121
121
RX/DT
pin
120
Note: Refer to Figure 24-3 for load conditions.
122
TABLE 24-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid
—
—
—
40
20
20
ns
ns
ns
121
122
TCKRF
TDTRF
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
FIGURE 24-19:
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TX/CK
pin
125
RX/DT
pin
126
Note: Refer to Figure 24-3 for load conditions.
TABLE 24-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CK ↓ (DT hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CK ↓ (DT hold time)
© 2009 Microchip Technology Inc.
DS39682E-page 333
MICROCHIP [ MICROCHIP ]
