PIC18F45J10 FAMILY
FIGURE 24-16:
SCLx
MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
93
91
90
92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 24-3 for load conditions.
TABLE 24-20: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start
condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns After this period, the
first clock pulse is
generated
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
2(TOSC)(BRG + 1)
ns
400 kHz mode
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
FIGURE 24-17:
MASTER SSP I2C™ BUS DATA TIMING
103
102
100
101
109
SCLx
90
106
91
92
107
SDAx
In
110
109
SDAx
Out
Note: Refer to Figure 24-3 for load conditions.
© 2009 Microchip Technology Inc.
DS39682E-page 331
MICROCHIP [ MICROCHIP ]
