PIC18F45J10 FAMILY
24.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 24-4:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
Q1
OSC1
CLKO
3
4
3
4
2
TABLE 24-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
1A
1
FOSC
External CLKI Frequency(1)
Oscillator Frequency(1)
External CLKI Period(1)
DC
4
40
25
MHz EC Oscillator mode
MHz HS Oscillator mode
TOSC
25
25
—
ns
ns
EC Oscillator mode
HS Oscillator mode
Oscillator Period(1)
250
2
3
TCY
Instruction Cycle Time(1)
100
10
—
—
ns
ns
TCY = 4/FOSC, Industrial
EC Oscillator mode
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
4
TOSR,
TOSF
External Clock in (OSC1)
Rise or Fall Time
—
7.5
ns
EC Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations.
All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption. All devices are tested to
operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input
is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
© 2009 Microchip Technology Inc.
DS39682E-page 319
MICROCHIP [ MICROCHIP ]
