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PIC18F24J10-I/SO 参数 Datasheet PDF下载

PIC18F24J10-I/SO图片预览
型号: PIC18F24J10-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
XORWF  
Exclusive OR W with f  
Syntax:  
XORWF f {,d {,a}}  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
Operation:  
(W) .XOR. (f) dest  
Status Affected:  
Encoding:  
N, Z  
0001  
10da  
ffff  
ffff  
Description:  
Exclusive OR the contents of W with  
register ‘f’. If ‘d’ is ‘0’, the result is stored  
in W. If ‘d’ is ‘1’, the result is stored back  
in the register ‘f’ (default).  
If ‘a’ is ‘0’, the Access Bank is selected.  
If ‘a’ is ‘1’, the BSR is used to select the  
GPR bank (default).  
If ‘a’ is ‘0’ and the extended instruction  
set is enabled, this instruction operates  
in Indexed Literal Offset Addressing  
mode whenever f 95 (5Fh). See  
Section 22.2.3 “Byte-Oriented and  
Bit-Oriented Instructions in Indexed  
Literal Offset Mode” for details.  
Words:  
1
1
Cycles:  
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Decode  
Read  
register ‘f’  
Process  
Data  
Write to  
destination  
Example:  
XORWF  
REG, 1, 0  
Before Instruction  
REG  
W
=
=
AFh  
B5h  
After Instruction  
REG  
W
=
=
1Ah  
B5h  
DS39682E-page 290  
© 2009 Microchip Technology Inc.  
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