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PIC18F24J10-I/SO 参数 Datasheet PDF下载

PIC18F24J10-I/SO图片预览
型号: PIC18F24J10-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
21.6 Program Verification and  
Code Protection  
21.7  
In-Circuit Serial Programming  
PIC18F45J10 family microcontrollers can be serially  
programmed while in the end application circuit. This is  
simply done with two lines for clock and data and three  
other lines for power, ground and the programming  
voltage. This allows customers to manufacture boards  
with unprogrammed devices and then program the  
microcontroller just before shipping the product. This  
also allows the most recent firmware or a custom  
firmware to be programmed.  
For all devices in the PIC18F45J10 family of devices,  
the on-chip program memory space is treated as a  
single block. Code protection for this block is controlled  
by one Configuration bit, CP0. This bit inhibits external  
reads and writes to the program memory space. It has  
no direct effect in normal execution mode.  
21.6.1  
CONFIGURATION REGISTER  
PROTECTION  
21.8 In-Circuit Debugger  
The Configuration registers are protected against  
untoward changes or reads in two ways. The primary  
protection is the write-once feature of the Configuration  
bits which prevents reconfiguration once the bit has  
been programmed during a power cycle. To safeguard  
against unpredictable events, Configuration bit  
changes resulting from individual cell-level disruptions  
(such as ESD events) will cause a parity error and  
trigger a device Reset.  
When the DEBUG Configuration bit is programmed to  
a ‘0’, the In-Circuit Debugger functionality is enabled.  
This function allows simple debugging functions when  
used with MPLAB® IDE. When the microcontroller has  
this feature enabled, some resources are not available  
for general use. Table 21-3 shows which resources are  
required by the background debugger.  
The data for the Configuration registers is derived from  
the Flash Configuration Words in program memory.  
When the CP0 bit is set, the source data for device  
configuration is also protected as a consequence.  
TABLE 21-3: DEBUGGER RESOURCES  
I/O pins:  
RB6, RB7  
2 levels  
Stack:  
Program Memory:  
Data Memory:  
512 bytes  
32 bytes  
© 2009 Microchip Technology Inc.  
DS39682E-page 247  
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